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DesignCon 2014

DesignCon2014

 

AFTER the show update:

Order a DVD of the Agilent Education Forum: www.agilent.com/find/DesignConDVD

Download the papers presented below by clicking the title.

 

Welcome Reception was at the Computer History Museum , Mt. View, CADesignCon 2014

Agilent displayed and demonstrated high speed/high performance Oscilloscopes, Bit Error Ratio Test (BERT) Solutions, Logic Analyzers, Protocol Analyzers, Boundary Scan Analyzer, Agilent EEsof EDA Software, and RF & Microwave Network Analyzers. This year we also revealed New Product Introductions at DesignCon to include our new J-BERT M8020A High-performance BERT, the new N1055A Time Domain Reflection/Time Domain Transmission (TDR/TDT) Solution, and the Agilent EEsof EDA Controlled Impedance Line Designer.

► DesignCon 2014 Best Paper Award Finalist
► “Touchstone® v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 Memory Interface Applications” in the Power and RF Design category


► “Mechanism of Jitter Amplification in Clock Channels” in the High Speed Design category


► “IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links” in the Interconnect Design and Test category

Agilent Papers:

13-TU1: Combined Hands-On Tutorial for Fixture Removal of 28Gbps Tx Measurements - with tech paper
• Speakers: Heidi Barnes (Agilent Technologies, Inc.), Jack Carrel (Xilinx, Inc.), Romi Mayder (Xilinx, Inc.), Mike Resso (Agilent Technologies, Inc.), Rob Sleigh (Agilent Technologies, Inc.)

8-TU2: Relating COM to Familiar S-Parameter Parametric to Assist 25Gbps System Design
• Speakers: Xiaoqing Dong (Huawei Technologies Company, Ltd.), Wenyi Jin (Xilinx, Inc.), Moore Mo (Huawei Technologies Company, Ltd.), Fangyi Rao (Agilent Technologies, Inc.), Geoff Zhang (Xilinx, Inc.)

9-TU3: Battle on the Chip: Embed vs. De-Embed? - Panel Discussion
• Speakers: Eric Kvamme (LSI Corporation), Greg LeCheminant (Agilent Technologies, Inc.), Mike Li (Altera Corporation), Chris Loberg (Tektronix, Inc.), Martin Miller (Teledyne LeCroy), Ransom Stephens (Ransoms Notes), Pavel Zivny(Tektronix, Inc.)

9-WE4: Mechanism of Jitter Amplification in Clock Channels - ► ► DesignCon 2014 Best Paper Award Finalist
• Speakers: Sammy Hindi (Juniper Networks, Inc.), Fangyi Rao (Agilent Technologies, Inc.)

8-WE5: IBIS AMI Modeling of Retimer and Performance Analysis of Retimer Based Active Serial Links - ► ► DesignCon 2014 Best Paper Award Finalist
• Speakers: Venkatesh Avula (LSI Corporation), Alfred Chong (Texas Instruments, Inc.), Liang Liu (Texas Instruments, Inc.), Makram Mansour (Texas Instruments, Inc.), Srikanth Pam (Texas Instruments, Inc.), Fangyi Rao (Agilent Technologies, Inc.)

11-WE5: Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of - DDR4 Memory Interface Applications - ► ► DesignCon 2014 Best Paper Award Finalist
• Speakers: Raymond Anderson (Xilinx, Inc.), Nilesh Kamdar (Agilent Technologies, Inc.), Romi Mayder (Xilinx, Inc.)

8-WE6: Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies
• Speakers: Yunong Gan (Broadcom Corporation), Fangyi Rao (Agilent Technologies, Inc.), Vivek Telang (Broadcom Corporation), Magesh Valliappan (Broadcom Corporation), Todd Westerhoff (SiSoft, Inc.), Dong Yang (Broadcom Corporation)

6-WE7: How PCB Design is Changing: Simulation and Design Techniques - Panel Discussion
• Speakers: Eric Bogatin (Bogatin Enterprises), Filip Demuynck (Agilent Technologies, Inc.), Michael Dunn (EDN), Scott McMorrow (Teraspeed Consulting Group, LLC), Chudy Nwachukwu (Isola Group), Lee Ritchey (Speeding Edge), David Wiens (Mentor Graphics, Inc.)

7-WE7: Powering the Next Mobile Generation: An Industry Overview of UFS - Panel Discussion
• Speakers: Kathy Choe Thomas (Samsung), Zachi Friedman (Arasan Chip Systems), John Geldman (Micron Semiconductor), Perry Keller (Agilent Technologies, Inc.), Janine Love (UBM Tech)

3-TH2: Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI
• Speakers: Amolak Badesha (Avago Technologies, Ltd.), Sanjeev Gupta (Avago Technologies, Ltd.), Ramana Murty (Avago Technologies, Ltd.), Zhaokai Yuan (Agilent Technologies, Inc.)

3-TH7: Optical System Technologies and Integration - Panel Discussion
• Speakers: Brice Achkir (Cisco Systems, Inc.), Eric Bogatin (Bogatin Enterprises), Mitchell Fields (Avago Technologies, Inc.), Greg LeCheminant (Agilent Technologies, Inc.), Janine Love (UBM Tech), Arlon Martin (Mellanox Technologies), Pavel Zivny (Tektronix, Inc.)

13-FR2: Higher Speed Ethernet: 40 Gb/s Operation Over Twisted-Pair Copper Cabling
• Speakers: Christopher DiMinico (MC Communications, Inc.), Ronald Nordin (Panduit Corporation), Harshang Pandya (Psiber Data), Mike Resso (Agilent Technologies, Inc.), Mike Sapozhnikov (Cisco Systems, Inc.)

13-FR3: De-Mystifying the 28 Gb/s SERDES Channel - Design to Measurement
• Speakers: Heidi Barnes (Agilent Technologies, Inc.), Jack Carrel (Xilinx, Inc.), Hoss Hakimi (Xilinx, Inc.), Mike Resso (Agilent Technologies, Inc.), Rob Sleigh (Agilent Technologies, Inc.)

Agilent Educational Forum:

DAY 1:  Wednesday, January 29; 8:30-12:40pm
S. No. Title Abstract Speaker
1 Overcoming MIPI physical layer challenges New physical standards are being developed by Mobile Industry Processor Interface (MIPI) Alliance standards body, which standardizes interfaces for mobile applications and designs. Additional capabilities and data rate extension will be added to the existing D-PHY and M-PHY specifications to push the performance envelope. A new C-PHY specification will also be created, which is based on a new 3-wire multi-level signaling scheme to achieve higher performance through higher bits/symbol. If you are developing or validating these new MIPI physical layers, you want to understand the new test challenges and solutions. Min Jie
2 PCI Express Progresses: Speed, Mobile, and Storage advancements PCI Express has become a ubiquitous standard in digital computer and communication systems that many designers today are familiar with. As the technology advances, pure speed in terms of data rate has to be balanced with practical cost effectiveness across this broad application footprint. This paper covers current and future electrical signal integrity challenges faced by designers using PCI Express technology both today and into the near future. In addition, it will discuss how PCI Express technology is expanding into mobile (MIPI) and data storage (NVM Express ) standards as engineers seek to apply PCI Express technology to an ever wider array of applications. Rick Eads 
3 Memory Technology Revolutions Driving Mobile and Cloud Computing A new generation of DRAM and mobile mass storage technologies are being created to enable the next generation of smartphones and tablets. Server class DRAM performance and SSD class mass storage capabilities for pocket sized battery powered devices will become the standard. Cloud servers will new memory technologies to serve an always-connected world. This session explains the technology underlying this revolution and the new design and test technologies required to enable it. Perry Keller
4 Simulation-measurement workflow for DDR compliance DDR electrical compliance testing is required for memory controllers and DRAMs to comply with JEDEC specification and to be interoperable among vendors. This paper discusses Agilent DDR3 and DDR4 compliance test applications using both pre-silicon simulated waveforms and post-silicon measured waveforms. When correlating simulation with measurement, one needs to consider the differences between simulated and measured waveforms, such as variable time-step vs fixed time step, continuous data-stream vs. burst type signaling, simulated DQ + DQS without CLK vs. captured waveforms DQ, DQS, CLK. Simulations usually use variable time-steps for higher efficiency, while measurements use a fixed time step. In addition the compliance test application needs to work with bursts of data, and needs to separate the write mode from the read mode and tri-state mode, using a preamble structure at the beginning of the data burst. This paper will discuss how to add the preamble structure to the simulation setup to generate the required DQ and DQS waveforms. Finally a simulation-measurement correlation methodology called “Waveform Bridge” is discussed where DQ and DQS waveforms in both pre-layout and post-layout simulations are used for DDR compliance test. Steve Chen
5 Trends in data communications and the related test challenges Today’s “connected life” is a huge revenue generator for the whole communications eco system. The business opportunity scales with the availability and quality of services for end users. Speed and latency of the transmitted data are the key enabler and bottleneck at the same time for communication. Users demand access to data and communication services at any time anywhere.
To capture more of these opportunities creates huge challenges for several industries. In particular speeding up users PCs and mobiles and extending battery life or getting data out of data centers via the public network to end users is a key concern to some industries.
This paper will outline what challenges are ahead in order to increase data throughput and what options the industry sees to solve them. Examples of increasing data throughput by choosing the most effective data format or by just increasing the clock speed will be discussed. Having the right tests and tools in place in order to enable or accelerate designs that lead to higher data throughput is also one of the industries’ concerns. Another one is the higher level of integration in the industry and the related difficulties to get the devices into the test mode. The paper will outline the trends in the test and measurement industry that target to help solve those existing challenges.
Michael Reser
DAY 2: Thursday, January 30; 8:30am-12:40pm
6 New 1 port Automatic Fixture Removal This paper discusses the recent advances in removing the effects of a fixture from measurements of non-coaxial devices. Historically, fixtures were either modeled using an EM simulator and then subsequently de-embedded from the measurement. Another alternative might be to design and fabricate a TRL calibration kit to move the calibration reference plane to the end of the fixture. Simulations can take a long time to compute and require accurate material properties and dimensions to create an accurate model. TRL cal kits require multiple standards to create a broad band accurate model. This new technique requires just one calibration standard: a fixture thru, an open fixture, or a shorted fixture to accurately measure and model the fixture in order to remove its effects from the measurement. These effects are not limited to loss and phase shift like some simple techniques, but also include mismatches, discontinuities, and even coupling for differential fixtures. Simply measuring an open fixture or package with this new technique is enough information to quickly and accurately remove its effects from the fixtured (packaged) device measurement. Bob Schaefer
7 The next generation in Oscilloscope User Interface While real time oscilloscope technologies have now pushed over 60 GHz in bandwidth, many of their user interfaces remain antiquated and difficult to use. Tasks as simple as changing statistics to see what you want to see, seem difficult in today’s oscilloscope user interfaces. Some user interfaces are as limited as to only support one grid. However, new user interface technologies are emerging. The new user interfaces make it easier to view your waveforms and solve your problems. This presentation will show Agilent’s offline capability and its new user interface, which will show the tools that are available in today’s emerging user interfaces. Min Jie
8 SFP+ transmitter compliance testing on real-time and sampling oscilloscopes Learn how to quickly verify host SFP+ devices for SFF-8436 specification compliance. What are the pitfalls? How can I save time? Also how to test QSFP+ and multiple SFP+ lanes. Alex Bailes, Bob Hasenick
9 Touchstone® v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 Memory Interface Applications Large port count (>100) Touchstone® v2.0 S-Parameter data formats with per port reference impedances are essential in designing the next generation of memory interconnects. Using DDR4 as an example this paper shows how Touchstone v1.0 format limitations can lead to erroneous or inaccurate results for SI and PI co-simulations and how they can be overcome using the new v2.0 format. In addition to reliable channel models, one also needs accurate representation of the memory controllers and memory modules. To simulate simultaneous switching noise (SSN), Power Aware IBIS v5.0 models are required. This paper will demonstrate the accuracy and efficiency of such models by examining a few examples. These models, combined with the interconnect models, can then be used in a transient (SPICE) simulator to analyze simultaneous switching noise and its effects on the design. Such an analysis allows one to identify problem areas, debug issues and optimize the design to meet specifications in a timely manner. Jian Yang
10 Breakthrough Developments in TDR/TDT Measurement Technology  TDR/TDT measurements can help engineers troubleshoot their designs quickly and easily. TDR helps identify the magnitude, nature, and location of impedance problems that can degrade system BER performance. As bit rates increase, TDR solutions must offer faster step speeds and higher bandwidth to accurately resolve and measure discontinuities for a given design. Impedance measurements (time-domain) can also be combined with Scattering parameters (frequency domain) to provide a more complete characterization of a high-speed digital design. The Agilent 86100D DCA-X offers intuitive and fully-integrated TDR/TDT/S-parameter tools that help designers troubleshoot and isolate impedance problems quickly and accurately.
In addition to TDR/TDT measurements on passive devices, impedance mismatch of transmitters and receivers may cause significant reflections, which may have a significant impact on signal integrity. Many high speed serial standards require impedance measurements of active devices for compliance. Most standards require that the devices be operating during measurements, because the impedance is different between the power on and off states. The impedance measurement in the powered on and operating state is called Hot TDR. The Agilent ENA Option TDR offers an innovative method to measure Hot TDR.
 
Rob Sleigh, Yoji Sekine

SI TextbookThe "Signal Integrity Characterization Techniques" textbook from authors Mike Resso and Dr. Eric Bogatin is now available as a free download.