Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs
1 Hour | Webcast - recorded | Where & When
PCI Express represents the latest in high performance interconnect technologies in wide use within the computer and communications industries. As PCI Express provides an extension of the PCI specification, it is also being used broadly within many embedded applications including automotive, medical, and within industrial applications. After attending this seminar you will have a clearer understanding of tools and techniques you can apply to help validate the physical layer performance of your PCI Express link. You will also learn about the new capabilities and test challenges brought on by the latest PCIe 3.0 standard operating at 8GT/s and what implications that has for designs based on the 1.1 or 2.0 standard.
Who should attend:
Digital engineers involved in hardware design and signal integrity analysis who are using or will use PCI Express compliant signaling.
PCI Express and PCIe are U.S. registered trademarks and/or service marks of PCI-SIG.
Where & When
|Price||Date(s)||Location||For more information|
2011-05-19 15:30 — 16:30
|At your desk||Enroll/View the recording of the live broadcast|
Prices shown are list prices and are subject to change without notice.
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