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Testing DDR Memory; How On-Chip DFT Helps
This paper discusses DDR memory testing challenges we see today, and how the adoption of DFT capabilities pays off in higher test coverage, better diagnostics and reduced programming/support time.

Article 2012-04-17

PDF PDF 530 KB
Boundary-Scan Advanced Diagnostic Methods
This paper illustrates how usage of boundary scan circuit information and predictive analysis of potential assembly faults will provide more precise and accurate diagnostic information.

Article 2012-04-17

PDF PDF 1.20 MB
Silicon Nails increases your test coverage

Demo 2011-07-22

How to build a fixture for use with the Agilent Cover-Extend Technology
Cover-Extend Technology is Agilent’s latest limited access solution for in-circuit test. This paper documents the necessary information for a fixture vendor to build a Cover-Extend fixture.

Application Note 2011-06-24

PDF PDF 1.09 MB
Principal Component Analysis-Based Compensation for Measurement Errors
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE

Article 2010-12-10

PDF PDF 1.10 MB
Surviving State Disruptions Caused by Test: the "Lobotomy Problem"
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE

Article 2010-12-10

PDF PDF 402 KB
Solutions for Undetected Shorts on IEEE 1149.1 Self-Monitoring Pins
This paper presents the problem of undetected shorts on IEEE 1149.1 compliant self-monitoring pins, and potential mitigating solutions.

Article 2010-12-10

PDF PDF 789 KB
The Proposed IEEE Test Standards
There is a resurgence of interest in Boundary Scan and Built in Self Test (BIST) initiatives to be part of IEEE standards. This article explains the IEEE standard and their benefits to the industry. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend

Article 2010-10-20

PDF PDF 2.83 MB
Limited Access Tools Improve Test Coverage
Smaller test pads and shrinking board sizes are posing new challenges, and driving innovations to overcome limited access with new test solutions. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend

Article 2010-10-20

PDF PDF 275 KB
Comparing Boundary Scan Methods White Paper
The need for reusable tests is driving standalone boundary scan-ICT integration. This article first appeared in the September 2009 issue of Circuits Assembly and is reprinted with kind permission.

Article 2010-06-09

PDF PDF 2.68 MB
Medalist VTEP v2.0 Powered, with Cover-Extend technology
This brochure provides an overview of Cover-Extend under the VTEP v2.0 Powered vectorless test suite

Brochure 2010-04-06

PDF PDF 237 KB
Medalist i3070 In Circuit Test – Utilizing the most comprehensive Limited Access
This article introduces the seven most prominent and effective limited access tools on the Agilent Medalist i3070 ICT, collectively known Super 7 suite.

Application Note 2009-03-06

PDF PDF 342 KB
High Node Count Fixturing Solutions for Agilent Short-Wire Test Fixtures
This paper discusses problems encountered in building large, high node count vacuum actuated test fixtures for the Agilent 3070 family of board test systems.

Application Note 2008-04-30

PDF PDF 67 KB
Maximising Test Coverage with Agilent Medalist VTEP v2.0
This paper describes how to get the most from Agilent Technologies’ industry-leading vectorless test innovation, the Medalist VTEP v2.0 which is a suite of solution comprising VTEP, iVTEP and NPM.

Application Note 2007-04-17

PDF PDF 227 KB
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“Shotgunning”, a Bad Fit for Lead-Free Test
Shotgunning, a common repair technique in functional test, will be negatively affected by lead-free processes. This article explores the technique and draws broad conclusions regarding the impact of lead-free on electronics manufacturing test

Application Note 2006-02-07

PDF PDF 44 KB
In-circuit Testing of Low Voltage Devices
Core technical document summarizing issues regarding the testing of low voltage devices on the 3070 and i5000, including updated Safeguard information.

Application Note 2005-05-25

PDF PDF 172 KB
Test and Inspection as Part of the Lead-free Manufacturing Process
The paper addresses issues that will impact defect levels and defect spectrum during the transition to lead-free manufacturing. It also addresses different test and inspection systems’ readiness to test lead-free printed circuit board assemblies.

Application Note 2005-02-22

PDF PDF 421 KB
The Importance of Test and Inspection When Implementing Lead-Free Manufacturing
Many papers, articles, and studies have been written about process issues, reliability issues, repair issues, and the merits of different alloys. This paper addresses the impacts on test and inspection when going lead-free.

Application Note 2004-08-20

PDF PDF 260 KB
Using Lead-Free PCB Finishes at Manufacturing In-circuit Test Stage
The purpose of this document is to share experiences and educate engineers regarding different PCB surface finishes and the specific changes required in the PCB build process to allow for ICT.

Application Note 2004-08-08

PDF PDF 102 KB
Test Coverage: What Does It Mean when a Board Test Passes?
Originally presented at the 2002 International Test Conference -- Characterizing board test coverage as a percentage of devices or nodes having tests does not accurately portray coverage, especially in a limited access testing environment.

Application Note 2003-07-28

PDF PDF 266 KB
Testing Transformers on Unpowered Systems
This paper explains how to test basic analog parts, using unpowered systems.

Application Note 2003-03-21

PDF PDF 10 KB
Boundary Scan Helps EMS Companies Cut Test Costs and Increase Revenues
Electronics Manufacturing Services (EMS) providers can utilize boundary-scan to reduce test cost expenses and also generate additional revenue opportunities.

Application Note 2003-03-01

PDF PDF 242 KB
Using Boundary Scan to Link Design and Manufacturing Test
By leveraging boundary-scan tests generated in Design and re-using them at Manufacturing Test, manufacturers can produce long-term benefits in terms of lower costs, greater efficiencies and higher quality products.

Application Note 2003-03-01

PDF PDF 502 KB
What to Consider When Selecting the Optimal Test Strategy
This paper addresses several issues for selecting the optimal inspection strategy, presenting data from many studies that Agilent has performed in the quest to find the optimal test / inspection strategy.

Application Note 2003-03-01

PDF PDF 175 KB
Ground Bounce Basics and Best Practices
This article offers a description of the physical properties that result in ground bounce during board test.

Application Note 2003-01-28

PDF PDF 138 KB

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