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Testing DDR Memory; How On-Chip DFT Helps
This paper discusses DDR memory testing challenges we see today, and how the adoption of DFT capabilities pays off in higher test coverage, better diagnostics and reduced programming/support time.

Article 2012-04-17

PDF PDF 530 KB
Boundary-Scan Advanced Diagnostic Methods
This paper illustrates how usage of boundary scan circuit information and predictive analysis of potential assembly faults will provide more precise and accurate diagnostic information.

Article 2012-04-17

PDF PDF 1.20 MB
Principal Component Analysis-Based Compensation for Measurement Errors
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE

Article 2010-12-10

PDF PDF 1.10 MB
Surviving State Disruptions Caused by Test: the "Lobotomy Problem"
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE

Article 2010-12-10

PDF PDF 402 KB
Solutions for Undetected Shorts on IEEE 1149.1 Self-Monitoring Pins
This paper presents the problem of undetected shorts on IEEE 1149.1 compliant self-monitoring pins, and potential mitigating solutions.

Article 2010-12-10

PDF PDF 789 KB
The Proposed IEEE Test Standards
There is a resurgence of interest in Boundary Scan and Built in Self Test (BIST) initiatives to be part of IEEE standards. This article explains the IEEE standard and their benefits to the industry. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend

Article 2010-10-20

PDF PDF 2.83 MB
Limited Access Tools Improve Test Coverage
Smaller test pads and shrinking board sizes are posing new challenges, and driving innovations to overcome limited access with new test solutions. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend

Article 2010-10-20

PDF PDF 275 KB
Comparing Boundary Scan Methods White Paper
The need for reusable tests is driving standalone boundary scan-ICT integration. This article first appeared in the September 2009 issue of Circuits Assembly and is reprinted with kind permission.

Article 2010-06-09

PDF PDF 2.68 MB