J-BERT N4903B high-performance serial BERT

N4903B J-BERT high-performance serial BERT up to 7 Gb/s and 12.5 Gb/s with complete jitter tolerance

Stato del Prodotto:	Attualmente ordinabile \| Attualmente supportato

Key Specifications

Data rates 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector. Option to extended data rate to 14.2 Gb/s for pattern generator.
>0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, triangular and arbitrary SSC and residual SSC
Excellent signal performance and sensitivity
Built-in clock data recovery with tunable and compliant loop bandwidth
Half-rate clocking with variable duty cycle for forwarded clocked devices
Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture
PRBS and pattern with 60 block pattern sequencer
All options are retrofittable and upgrade from N4903A possible

Data Sheet
2009-10-19 | PDF 1.38 MB

Description

The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices.

It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5Gb/s or 14.2 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:

PCI Express®
SATA/SAS
DisplayPort
USB SuperSpeed
Fibre Channel
QPI
HyperTransport
Memory buses, such as fully buffered DIMM2
Backplanes, such as CEI
10 GbE/ XAUI
XFP/XFI, SFP+

Jitter setup screen of J-BERT N4903B	Automated jitter tolerance characterization

Quick eye digram and mask test	BERT scan with RJ/DJ separation

J-BERT N4903B key benefits:

Accurate characterization is achieved with clean signals from the pattern generator, which features exceptionally low jitter and extremely fast transition times. Built-in and calibrated jitter source allow accurate jitter tolerance testing of receivers.

Test set-up is simplified significantly, because the J-BERT N4903B is designed to match serial bus standards optimally with its differential I/Os, variable voltage levels on most outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns.

Faster test execution is possible with J-BERT’s automated jitter tolerance tests fast total jitter measurements.

The J-BERT N4903B is a long-term investment which is configurable for today’s test and budget requirements but also allows upgrades from the N4903A model, and later retrofit of all options and full speed when test needs change.

Read the latest press release

PCIe is a trademark and PCI Express is a registered trademark of PCI-SIG