83496B Optical/Electrical Clock Recovery Module With Phase Noise Analysis Capability

Optical clock recovery (option 101 only)

• Inputs & outputs: 9/125 µm (single-mode) to 62.5/125 µm (multimode)
• Wavelength range: 1250-1650 nm (single-mode), 750-1330 nm (multimode)
• Minimum optical modulation amplitude: -11 dBm (1310/1550 single-mode), -10 dBm (1310 multimode), -8 dBm (850 multimode)

Electrical clock recovery (option 100 only)

• Inputs: single-ended or differential, 3.5 mm (m) connectors
• Outputs (option 100 only): single-ended or differential, 3.5 mm (m) connectors
• Minimum electrical input level: 75 mV_pp

Continuous unbanded tuning from 50 Mb/s up to 14.2 Gb/s

• Golden PLL operation (option 300) with a tunable loop bandwidth from 15 KHz to 10 MHz
• Ultra low residual jitter: < 300 fs rms (characteristic at 10 Gb/s)
• High gain for tracking spread-spectrum signals
• Phase noise analysis of clock or data signals

Compatibility

• 86100C Infiniium DCA-J Mainframe
• 86100D Infiniium DCA-X Mainframe

The 83496B Clock Recovery Module with Phase Noise Analysis provides increased eye-mask and jitter measurement accuracy with breakthrough performance in clock recovery circuitry. It provides ideal performance for waveform analysis with the 86100C Digital Communications Analyzer and can derive a clock from signals with rates as low as 50 Mb/s-14.2 GB/s*, and any rate in between. At under 300 femtoseconds rms, the residual jitter of the output clock is virtually negligible, allowing accurate measurements of very low levels of signal jitter. Jitter spectrum and phase noise analysis on clock and data signals is available through a downloadable external application (www.agilent.com/find/jtf)

* Requires 86100C DCA-J Firmware Revision A.08.10 or later

System configuration:

All 86100A/B/Cs and the 86100D in the ETR configuration have a internal trigger connections between modules and the mainframe. 86100Ds with option STR do not and therefore require an external cable (such as P/N 5062-6690) from the clock recovery module’s recovered clock output to the mainframe’s trigger input.