PCIe™ Physical Layer Testing

Get Ready for PCI Express 2.0 Device Characterization on the physical layer

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Increasing speed rate for PCI Express 2.0 is driving designs to new dimensions. Validating and testing of PCI Express devices at the physical layer is getting more and more challenging for today’s engineers.

PCI Express device characterization on multiple lanes and pre-emphasis

The important test requirement is measuring BER on the PCI Express I/O ports. The PCI Express design works in loop-back mode for characterization.

For testing and validation the PCI Express receiver site, the ParBERT 81250 is able to provide a very clean data signal with low noise and jitter. Conversely, ParBERT is flexible in creating a differential de-emphasized data signal including large eye closure by jitter modulation. For data analysis, ParBERT provides differential connectivity and CDR. The ParBERT 81250, in combination with the Agilent 81150A, can modulate a defined jitter amplitude top test minimum receiver eye width characteristics and jitter tolerance measurements. The proper jitter spectrum is achieved by filtering the white noise of the 81150A with the PCIe 2.0 psecific filter set 15431A. Spread spectrum clocking is achieved by frequency modulation of clock and data. For testing PCI Express x4, x8 and x16, multiple stimulus channels can be configured for functional and stress test on multiple channels.

PCI Express device characterization and compliance on a single lane, with SSC and jitter tolerance testing

The Agilent N4903A high-performance serial BERT (J-BERT) allows to generate training sequences, compliance pattern and SKP frames to bring a single-lane PCI Express design into loop back mode.

A receiver’s jitter tolerance can be tested with the N4903A’s built-in and calibrated jitter sources. Sinusoidal Jitter, Bounded Random Jitter can be combined to inject a worst-case stressed eye. In addition PCIe 2.0 defines a specific random jitter profile which is generated by the 81150A and the filter set 15431A. Intersymbol interference can be emulated with the N4903A’s interference channel. SSC clocks can be provided from the N4903A without injecting signals from an external source. A 100 MHz reference clock is easily set up with the sub-rate clock output of the N4903A.

Required Features for PCI Express characterization

• Differential de-emphasized TS1, TS2, SKP, compliance patterns for RX data detection
• Jitter modulation for minimum detectable eye width jitter tolerance
• Frequency modulation @ clock/data in order to emulate spread spectrum clocking (SSC)
• Single and Multiple lane stimulus allows to measure delay between PCI Express lanes x4, x8, x16
• Sequence pattern supplies PCI Express training sequences setup to set device into loop-back mode
• Differential analysis with CDR needed for BER measurement
• Speed rate up to 7 Gbit/s to support PCI Express II

E4875PCI PCI Express Fast Start-Up Kit:

Agilent provides a PCI Express Demo Kit that helps every engineer who needs to do Physical Layer Tests on a PCI Express device with an Agilent ParBERT 81250 faster.

The demo kit for ParBERT 81250 contains:

• CD ROM with 81250 ParBERT settings and pattern segments
• Product Note: "Next Generation I/O Bus PCI Express BER Test Solution"
• Set-up Guide Supplement: Creating PCI Express bit streams for BER testing(P/N: E4875-90010)
• Set-up Guide for ParBERT (P/N: E4875-90011)
• Intel Compliance Base Board
• PCI Express x16 Graphic Card (OEM)
• Power Supply (OEM)
• Contact Information
• 1 year warranty

Related Products/Solutions

In combination with Agilent 86100 Infinium DCA-J these BERTs are the most comprehensive and accurate jitter Tolerance and Analysis solution available

• Overview PCI Express Solutions from Agilent
• ParBERT 81250
• J-BERT N4903A High-Performance Serial BERT
• 81150A Pulse Function Arbitrary Noise Generator
• 81134A Pulse Pattern Generator
• E2960 Protocol Analyzer and Protocol Exerciser for PCI Express
• Infiniium DCA 86100 Series Oscilloscopes

The Agilent ParBERT 81250 platform provides standard compliant training sequences, compliance patterns and SKP frames to stimulate PCI Express design. The bit flow can be controlled and combined by the ParBERT sequence editor to a complex data flow including loop level control.

^{PCI Express and PCIe are registered trademarks of PCI-SIG}

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