PCI Express Device Characterization with BERTs

Required Features for PCI Express

• Differential de-emphasized TS1, TS2, SKP, compliance patterns for RX data detection
• Jitter modulation for minimum detectable eye width jitter tolerance
• Frequency modulation @ clock/data in order to emulate spread spectrum clocking (SSC)
• Single and Multiple lane stimulus allows to measure delay between PCI Express lanes x4, x8, x16
• Sequence pattern supplies PCI Express training sequences setup to set device into loop-back mode
• Differential analysis with CDR needed for BER measurement
• Speed rate up to 7 Gbit/s to support PCI Express II

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  2008-10-07 | PDF 599 KB

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