PCI Express Device Characterization with BERTs

제품상태:	주문가능 \| 기술지원 가능

Differential de-emphasized TS1, TS2, SKP, compliance patterns for RX data detection
Jitter modulation for minimum detectable eye width jitter tolerance
Frequency modulation @ clock/data in order to emulate spread spectrum clocking (SSC)
Single and Multiple lane stimulus allows to measure delay between PCI Express lanes x4, x8, x16
Sequence pattern supplies PCI Express training sequences setup to set device into loop-back mode
Differential analysis with CDR needed for BER measurement
Speed rate up to 7 Gbit/s to support PCI Express II