Serial ATA (SATA) RSG and PHY test solutions
Key Features & Specifications
- Test automation
- Automated RSG test setup calibration
- RSG setup also used for PHY and TSG tests
- Test solutions for compliance, debug and compliance testing
In 2006 the SATA-IO started to define a receiver test. This receiver test specification is finished and a receiver test is now required.
Agilent is offering three different RSG test solutions to fit SATA RSG test need from BER based characterization to FER based compliance testing.
Automated characterization and compliance testing
Jitter Tolerance curves are key to understand the real jitter performance of a receiver. The N5990A Test Automation Platform offers with option -103 not only automated RSG compliance testing, but also automated receiver characterization including jitter tolerance. The N5990A automation software controls the whole 81134A Pulse Pattern Generator based SATA test setup. Click here to learn more about the N5990A Test Platform.
Cost-effective compliance test setup
This test setup is based on the renowned 81334A Pulse Pattern Generator and the widely used DSO80000 Oscilloscope series. It is intended for engineers looking for an economic way to test the compliance of their devices. This setup uses a Crescent Heart SATA probe for FER counting. Click to see cost-effective compliance test setup.
Value setup with debug capabilities
Like the cost-effective setup, this setup is based on the 81334A Pulse Pattern Generator and the DSO80000 Oscilloscope series. The Agilent 16900 series logic analyzer with the N4219B SATA probe is used for FER counting. The logic analyzer allows to debug a device which failed the RSG compliance test. It is intended for engineers looking for a way to test the compliance of their devices as well as to debug a failed device. Click here to see value setup with debug capabilities.
BERT setup for silicon vendors
This setup is based on the N4903A J-BERT. It has been especially developed for the characterization of the receiver of a SATA device. This BERT based measurements are performed without the effects of retiming, coding and scrambling to ensure extensive physical layer characterization of the receiver cell. The device is tested in a near-end loop-back mode1. Click here to see BERT setup for silicon vendors
1) The test requires, that the device can be set into a near-end loopback via device custom interface.
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