The W1717 Hardware Design Kit is a hardware design personality that adds on to the base W1461BP SystemVue Communications Architect. It provides a fixed-point simulation library (formerly available separately as the W1903EP) and generates synthesizable, hierarchical, RTL-level Verilog and VHDL. When configured with 3rd party synthesis tools, the W1717 provides a path to implementation, and automatically creates a verification wrapper for polymorphic model-based design flow. Finally, the W1717 enables hardware-in-the-loop (HIL) real-time co-verification over a fast PCIe interface, for select FPGA families.
The Verilog and VHDL generated by the W1717 Hardware Design Kit is transportable between design targets, and provides a great head-start for rapid prototyping and software-defined radio (SDR).
- Read more: FPGA Prototyping Using SystemVue
Why should I buy the W1717 Hardware Design Kit?
- Fidelity: Quickly account for bit-true hardware effects prior to targeting, while still at the architecture level, for better BB-RF partitioning
- Productivity: Integrate your proprietary, hand-optimized HDL blocks or import IP cores from external sources, such as Xilinx CoreGen
- Vendor-Neutrality: Generate target-neutral RTL that is transportable between hardware vendors
- Tool Connectivity: Rapid-prototyping with direct integration to Xilinx ISE, Altera Quartus II and other synthesis tools
- Real-time Verification: Verify and accelerate algorithms with Hardware-in the-Loop (HIL) co-simulation with Xilinx Virtex 6 families over PCIe (such as the ML-605 development board)
- True Model-based Design: Verify and debug FPGA hardware algorithms in the presence of RF EDA models, Measurement waveforms, and simulation-based wireless Standards references at every level of abstraction. Expand your baseband coverage to RF-BB co-design.
Who will benefit from the W1717 Hardware Design Kit?
- System architects can avoid guesswork and make more optimal design choices and partitions for high-performance PHYs. HDL generation enables rapid prototyping of working hardware, for faster design maturity and evolution.
- HDL hardware designers can verify hardware designs more easily against RF models, Test Equipment waveforms, and Standards-compliant baseband reference IP.
- Software-defined Radio (SDR) architects and designers responsible for multiple disciplines will appreciate the productivity gains of proven, HDL generation for routine blocks that are good quality, human readable, and target neutral.
What’s Included in the W1717 Hardware Design Kit?
- Fixed-point library containing 45 bit-true, cycle accurate models. Enables fixed-point datatype and simulation mode with block-level/pin-level fixed point histograms and “red-x” overflow/underflow analysis.
- Integration of custom libraries of hand-generated HDL and external IP cores, such as Xilinx CoreGen
- HDL code generation of RTL-level VHDL/Verilog, complete with design hierarchy, system-level test bench wrappers, test vectors, intelligent creation of clock ready and enable signals
- Polymorphic model instantations added for each installed HDL simulator, such as Aldec Riviera-PRO, or Mentor Modelsim SE, enabling easy model-based scripting and co-simulation, with verification-in-place.
- Direct integration of synthesis tools such as Xilinx ISE and Altera Quartus II from the SystemVue GUI
- Hardware-in-the-Loop co-simulation. Bring real-time Virtex 6 acceleration into SystemVue using development boards such as the ML-605 over PCIe.
Figure 1. The W1717 fixed-point library provides over 45 signal processing blocks that are ready for target-neutral HDL code generation. It also provides underflow/overflow diagnostics that assist baseband architects in troubleshooting bit-true finite=precision effects.
Figure 2. The W1717 Hardware Design Kit produces human-readable, target-neutral VHDL or Verilog that can be simulated, modified, or directly synthesized into an FPGA implementation to assist rapid prototyping.
Figure 3. The W1717 Hardware Design Kit enables a path to FPGA hardware realization. It also maintains model polymorphism at each of level of abstraction, allowing convenient, model-based verification from the system level.
The W1717 Hardware Design Kit includes the fixed-point library required for HDL code generation, and adds to any SystemVue Environment.
The W1717 Hardware Design Kit is included in these bundles:
Follow the link below to view all SystemVue configurations:
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