IEEE 1149.1 InterconnectPlus Boundary Scan
Key Features & Specifications
- Compliant to IEEE 1149.1 standard
Performs following tests :
Scan Path Integrity Test
IEEE 1149.1 is a standard approved by the Institute of Electrical and Electronics Engineers (IEEE) in 1990 that allows testing of a device without the need to know the function of the core logic of the device. This is achieved in large part through the use of a chain of registers in series; each register associated with a signal pin of a device. This boundary register is located between the core logic of the device and the pin of the device leading to the outside of the device package. The behavior of these boundary registers are controlled by what is called the TAP controller. This architecture is implemented fully within the silicon of the device. (Fig 1)
By connecting two or more boundary scan enabled devices together (Fig 2), a inter-connection of nodes is created. In manufacturing, testing revolves around finding short-circuit and open-circuit defects and this is achieved through the pumping of specific sequence of bits through this interconnection of nodes between ICs. Because of the specific nature of the input patterns, a specific pattern can, in turn be expected at the output; failing which it will indicate the nature and the location of the defect.
The driving and receiving of signals can be done by the boundary registers and therefore negates the need for physical test access for interconnect nodes.
Implementation of IEEE 1149.1 on Agilent ICT system means having the ability to generate tests in accordance to that standard automatically. A greater advantage would be the ability to test non boundary scan nodes in tandem with boundary scan nodes and hence have a fuller test coverage on the board. Because of this “native-to-ICT” implementation, it delivers a more potent solution to the user.
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