Accurate PCI Express® 3.0 Receiver Characterization
Key Features & Specifications
Key features required for PCIe 3.0 receiver test:
- Automated stress calibration software
- Emulation of PCIe 3.0 calibration channels
- Injection of PCIe 3.0 compliant sinusoidal interference (S.I.)
- Generation of two-tone periodic jitter with jitter sweep, random jitter
- Stressed sensitivity and jitter tolerance test
- Pre- and post-cursor de-emphasis
- Link training suite based on J-BERT's pattern sequencer
- Multiplying PLL for 100MHz reference clock with SSC (mother board test)
Error counting in loopback mode while SKP Ordered Set length varies
Get Ready for PCI Express 3.0 Receiver Characterization
To learn more about Agilent offering for testing PCI Express please click here.
Accurate PCI Express 3.0 Receiver Characterization
In 2010 the base specification for the PCI Express 3.0 interface was released by the PCI-SIG ®.
The transmission rate of 8 GT/s causes significant challenges for the design and test of ASICs, chips and boards.
Receiver testing is normative now, while in the past it was just informative.
Agilent offers a test set for accurate characterization of PCI Express 3.0 receiver ports for R&D and validation test.
What are the Key Challenges of PCI Express 3.0 Receiver Test?
Transmitting 8 GT/s over traditional PC board traces causes significant signal degradations. The receiver test ensures that the receiver under test can detect bits properly (at a BER level of 10-12) at worst-case stress conditions. For PCI Express 3.0 receiver test a stressed voltage eye and a stressed jitter eye test is defined by the base specification. The test challenges include optimizing transmit and receive equalization with 3 taps, emulating three different lengths of calibration channels, and device link training with 128/130 bit coded pattern sequences, and specific periodic and random jitter conditions. However, the most challenging requirement is to implement the new procedure for calibrating PCI Express 3.0 compliant stress conditions as a receiver would see them after applied equalization. This procedure requires post-processing of signals captured at an accessible test point.
What does Agilent offer?
Agilent's complete and accurate receiver test solution is based on the J-BERT N4903B high-performance serial BERT, the N4916B de-emphasis signal converter, the 81150A/81160A pulse function arbitrary noise generator, an Infiniium 90000 X-Series high-performance oscilloscope, new accessories and new N5990A test automation software. Agilent supports RX test of ASICs (according to the base specification) and RX test of add-in cards and motherboards (according to the CEM specification)
Test setup description (example shows ASIC test according base specification):
- J-BERT N4903B pattern generator provides built-in calibrated jitter and differential-mode Sinusoidal Interference (S.I.) sources, ref. clock and Spread Spectrum Clocking (SSC). Error detector with built-in Clock Data Recovery (CDR).
- N4916B adds pre- and post-cursor de-emphasis (it is transparent to jitter from J-BERT and tolerates non-balanced patterns)
- 81150A/60A source used for adding 120 MHz common mode S.I.
- N4915A-014 offers PCI Express 3.0 compliant calibration channels and combiners
- N5990A test automation software provides PCI Express 3.0 automated stress calibration, RX tests and link training suite
- The RX test setup can be modified to support also add-in card and motherboard test (e.g. N4880A reference clock multiplier)
Key benefits include:
- Accurate and repeatable receiver test results are possible by the stress calibration software, adjustable pre-and post-cursor de-emphasis, J-BERT’s built-in PCIe 3.0 compliant jitter and sinusoidal interference sources, SJ-sweep functionality and PCIe 3.0 compliant calibration channels
- Support of common and separate reference clock designs by the ability to ignore SKP Ordered Set length changes (Requires J-BERT N4903B SW 7.4 or later)
- Higher R&D efficiency by the unique stress calibration software (based on seasim software) and the link training suite which controls J-BERT's pattern sequencer to bring the device under test into loop back mode easily
- Lower investment by using Agilent instrumentation for testing multiple gigabit bus interfaces, such as USB3, SATA, QPI and Hypertransport
Recommended Agilent Receiver Test Setup (for add-in cards & motherboard test according CEM specification):
J-BERT N4903B high-performance serial BERT (12.5 G J-BERT with options C13, J10, J11, J20)
- Handling of SKP Ordered Set length changes (requires N4903B SW 7.40 or later and option A02)
- N4916B de-emphasis signal generator
- N4880A reference clock multiplier (only for motherboard test)
- N5990A test automation software (same options as for base spec testing)
- 90000A series or 90000 X-series oscilloscopes
Recommended Agilent Receiver Test Setup (for ASIC test according base specification):
J-BERT N4903B high-performance serial BERT. Recommended configuration for PCIe 3.0
- 12.5 G BERT with options C13, J10,J11, J20. Add option A02 for SKPOS handling
- SJ-sweep - free software update
- N4915A-014 PCIe 3.0 calibration channels
- N4916B de-emphasis signal generator
- 81150A or 81160A pulse function arbitrary noise generator
N5990A test automation software, possible options:
- Opt.101 PCIe receiver test including stress calibration
- Opt.301 PCIe 3.0 link training suite
- Opt.011 Upgrade of Opt.101 to current revision
90000A series or 90000 X-series oscilloscopes
PCI-SIG, PCI Express and PCIe are registered trademarks of PCI-SIG
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