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    <title>Agilent Technical Forums: Message List - Logic and protocol analyzers - Applications</title>
    <link>http://www.home.agilent.com/owc_discussions</link>
    <description>Most recent forum messages</description>
    <language>en</language>
    
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    <pubDate>Sat, 18 May 2013 03:04:12 -0600</pubDate>


    <item>

        <title>Re: SPI bus decoding ?</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=108133&amp;tstart=0#108133</link>

        

        
            <description><![CDATA[Back in the Dark Ages, SPI was limited to 8MHz. Now, of course, like everything else, it goes much faster. There are no faster solutions for the Logic Analyzer, but there are several families of Agilent Oscilloscopes that support SPI with HW-based...]]></description>
        

        <pubDate>Fri, 17 May 2013 15:46:34 -0600</pubDate>

        

        <jf:creationDate>Fri, 17 May 2013 15:46:34 -0600</jf:creationDate>
        <jf:modificationDate>Fri, 17 May 2013 15:46:34 -0600</jf:modificationDate>
        <jf:date>May 17, 2013</jf:date>
        <jf:author>algoss</jf:author>
        <jf:replyCount>0</jf:replyCount>
    </item>


    <item>

        <title>Re: SPI bus decoding ?</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=108121&amp;tstart=0#108121</link>

        

        
            <description><![CDATA[ALD HW solution is really good, but limited to 8MHz SPI clock maximum. <br />...]]></description>
        

        <pubDate>Fri, 17 May 2013 00:41:31 -0600</pubDate>

        

        <jf:creationDate>Fri, 17 May 2013 00:41:31 -0600</jf:creationDate>
        <jf:modificationDate>Fri, 17 May 2013 00:41:31 -0600</jf:modificationDate>
        <jf:date>May 17, 2013</jf:date>
        <jf:author>Alx</jf:author>
        <jf:replyCount>1</jf:replyCount>
    </item>


    <item>

        <title>Timing Sync between two N5306A blades of an N5541A-N2X</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=105394&amp;tstart=0#105394</link>

        

        
            <description><![CDATA[I am using my company's Agilent N5306A logic analyzer for the first time.  There are two blades in the N5541A-N2X chassis.  I'd need to synchronize the timing of two PCIe probes from this box.  Assuming that I can only have one probe on each blade, what...]]></description>
        

        <pubDate>Thu, 13 Dec 2012 13:42:30 -0700</pubDate>

        

        <jf:creationDate>Thu, 13 Dec 2012 13:42:30 -0700</jf:creationDate>
        <jf:modificationDate>Thu, 13 Dec 2012 13:42:30 -0700</jf:modificationDate>
        <jf:date>Dec 13, 2012</jf:date>
        <jf:author>tomDoster</jf:author>
        <jf:replyCount>0</jf:replyCount>
    </item>


    <item>

        <title>Re: E2969A software and test suites</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=105184&amp;tstart=0#105184</link>

        

        
            <description><![CDATA[Windows 7 not being supported is not a problem, I have one XP license available; I have just realized that<br />...]]></description>
        

        <pubDate>Thu, 29 Nov 2012 13:28:19 -0700</pubDate>

        

        <jf:creationDate>Thu, 29 Nov 2012 13:28:19 -0700</jf:creationDate>
        <jf:modificationDate>Thu, 29 Nov 2012 13:28:19 -0700</jf:modificationDate>
        <jf:date>Nov 29, 2012</jf:date>
        <jf:author>latech</jf:author>
        <jf:replyCount>0</jf:replyCount>
    </item>


    <item>

        <title>Re: E2969A software and test suites</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=105148&amp;tstart=0#105148</link>

        

        
            <description><![CDATA[The E2969A is not supported under Win7, either the 64 or 32 bit version.<br />...]]></description>
        

        <pubDate>Wed, 28 Nov 2012 05:18:55 -0700</pubDate>

        

        <jf:creationDate>Wed, 28 Nov 2012 05:18:55 -0700</jf:creationDate>
        <jf:modificationDate>Wed, 28 Nov 2012 05:18:55 -0700</jf:modificationDate>
        <jf:date>Nov 28, 2012</jf:date>
        <jf:author>algoss</jf:author>
        <jf:replyCount>1</jf:replyCount>
    </item>


    <item>

        <title>E2969A software and test suites</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=105118&amp;tstart=0#105118</link>

        

        
            <description><![CDATA[I have an E2969A PCIe PTC card with ver. 1.1.0.16 Windows tests for the PCIe 1.1 compliance tests<br />...]]></description>
        

        <pubDate>Mon, 26 Nov 2012 22:17:18 -0700</pubDate>

        

        <jf:creationDate>Mon, 26 Nov 2012 22:17:18 -0700</jf:creationDate>
        <jf:modificationDate>Mon, 26 Nov 2012 22:17:18 -0700</jf:modificationDate>
        <jf:date>Nov 26, 2012</jf:date>
        <jf:author>latech</jf:author>
        <jf:replyCount>2</jf:replyCount>
    </item>


    <item>

        <title>DIGITAL TEST SOLUTION</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=104395&amp;tstart=0#104395</link>

        

        
            <description><![CDATA[Dear Sir:<br />...]]></description>
        

        <pubDate>Sun, 14 Oct 2012 10:59:18 -0600</pubDate>

        

        <jf:creationDate>Sat, 13 Oct 2012 11:42:40 -0600</jf:creationDate>
        <jf:modificationDate>Sun, 14 Oct 2012 10:59:18 -0600</jf:modificationDate>
        <jf:date>Oct 14, 2012</jf:date>
        <jf:author>SOLT_guy</jf:author>
        <jf:replyCount>0</jf:replyCount>
    </item>


    <item>

        <title>Re: PCIe exerciser configuration</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=103897&amp;tstart=0#103897</link>

        

        
            <description><![CDATA[a) The cable is only required if you are connecting 2 frames together. In the original configuration, one of those cables came with every frame, and I never (ever) used the ones that I got.<br />...]]></description>
        

        <pubDate>Tue, 18 Sep 2012 13:46:54 -0600</pubDate>

        

        <jf:creationDate>Tue, 18 Sep 2012 13:46:54 -0600</jf:creationDate>
        <jf:modificationDate>Tue, 18 Sep 2012 13:46:54 -0600</jf:modificationDate>
        <jf:date>Sep 18, 2012</jf:date>
        <jf:author>algoss</jf:author>
        <jf:replyCount>0</jf:replyCount>
    </item>


    <item>

        <title>Re: PCIe exerciser configuration</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=103896&amp;tstart=0#103896</link>

        

        
            <description><![CDATA[I have acquired a PCIe analyzer system based on your recommendation, thank you. I am trying to understand the following:<br />...]]></description>
        

        <pubDate>Tue, 18 Sep 2012 13:15:14 -0600</pubDate>

        

        <jf:creationDate>Tue, 18 Sep 2012 13:15:14 -0600</jf:creationDate>
        <jf:modificationDate>Tue, 18 Sep 2012 13:15:14 -0600</jf:modificationDate>
        <jf:date>Sep 18, 2012</jf:date>
        <jf:author>latech</jf:author>
        <jf:replyCount>1</jf:replyCount>
    </item>


    <item>

        <title>Re: PCIe exerciser configuration</title>
        <link>http://www.home.agilent.com/owc_discussions/thread.jspa?messageID=103444&amp;tstart=0#103444</link>

        

        
            <description><![CDATA[The E2960 Protocol Analyzers were built using the RouterTester architecture. The frame and its connectivity to a PC are the same, but the analyzer cards are completely different, and can't coexist in the same frame as RouterTester. Some of the RouterTest...]]></description>
        

        <pubDate>Fri, 24 Aug 2012 06:18:48 -0600</pubDate>

        

        <jf:creationDate>Fri, 24 Aug 2012 06:18:48 -0600</jf:creationDate>
        <jf:modificationDate>Fri, 24 Aug 2012 06:18:48 -0600</jf:modificationDate>
        <jf:date>Aug 24, 2012</jf:date>
        <jf:author>algoss</jf:author>
        <jf:replyCount>2</jf:replyCount>
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