Thread: SPI bus decoding ?


Permlink Replies: 3 - Pages: 1 - Last Post: May 17, 2013 3:46 PM Last Post By: algoss
Alx

Posts: 17
Registered: 12/28/11
SPI bus decoding ?
Posted: Apr 5, 2012 12:05 AM
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Hi,
is it available any LA sw plug-in to decode (or Inverse assemble) for Serial Peripheral Interface bus (SPI) ?
I have some set-up with DAC (dig-to-analog converter) and Flash memory which needs to be debugged
(both are SPI).
Thanks
algoss


Posts: 518
Registered: 11/03/06
Re: SPI bus decoding ?
Posted: Apr 6, 2012 6:50 AM   in response to: Alx in response to: Alx
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Alx,

You have 2 ways you can go with this.

  • An optional (for pay) SW tool, called B4602A Signal Extractor, that will extract the serial SPI data, and display it as parallel SPI data. It won't do any protocol decode. The list price is about $2900. Information is in the LA help file.

  • A separate HW tool from Advanced Logical Devices (www.ald.com) that will convert the serial data stream to parallel, in hardware, allowing triggering, etc.

The HW solution is much better, and less expensive. Since it uses HW to parallelize the data it uses LA memory much more efficiently, and basic triggering is available.

If you have a specific protocol in mind on SPI that you want to decode, there is another optional SW tool, B4641A Protocol Development Kit. It allows you build write a decoder for your protocol. Used in conjunction with the ALD HW, it will allow protocol-level triggering on SPI 'packets'. It costs about $3900. Information on this is also in the LA help file.

Al
Alx

Posts: 17
Registered: 12/28/11
Re: SPI bus decoding ?
Posted: May 17, 2013 12:41 AM   in response to: algoss in response to: algoss
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ALD HW solution is really good, but limited to 8MHz SPI clock maximum.
How is better to do triggering/decoding when debugging modern SPI flash memories,
where SPI clock could be around 66MHz...85MHz and even 100MHz,
above that there are double and quad data transfer modes (when several data lines
are involved) ??
algoss


Posts: 518
Registered: 11/03/06
Re: SPI bus decoding ?
Posted: May 17, 2013 3:46 PM   in response to: Alx in response to: Alx
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Back in the Dark Ages, SPI was limited to 8MHz. Now, of course, like everything else, it goes much faster. There are no faster solutions for the Logic Analyzer, but there are several families of Agilent Oscilloscopes that support SPI with HW-based triggering, at up to 100 MHz. This would include the 3000X, 4000X, 7000B, 9000A families. There may be others. In every case, the signal going into the front of the scope is split out to an FPGA that handles the real-time triggering. Both protocol-based triggering and 'packet' level decode are available as options.

Al

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