Boundary Scan in a Nutshell
Testing at ICT requires “test access”. This refers to the testpoints (usually pads or vias) that are designed into the PCB, that probes can connect to in order to provide the electrical connectivity between the board-under-test and the tester. The test standard was formed by a consortium of companies in 1990 mainly to address the increasing lack of test access on PCB assemblies due to reducing PCB sizes and increasing functionalities being packed into the product.
IEEE 1149.1 (also known as Boundary scan) is a test standard that involves devices designed with shift registers placed between each device pin and the internal logic as shown in Figure 1. Each shift register is called a boundary scan cell. These boundary scan cells allow you to control and observe what happens at each input and output pin. When these cells are connected together, they form a data register chain, called the Boundary Register.
There are other registers within a boundary-scan device.
• An Instruction Register decodes instruction bits that allow the device to perform various functions.
• A Bypass Register provides a one-bit path that minimizes the distance between the scan input and the scan output.
• An Identification Register, called the IDCODE Register, identifies the device and manufacturer.
• Other designer-specified data registers typically perform internal test functions.
Boundary scan devices have a dedicated port, called the Test Access Port (TAP), that routes input signals to a controller, called the TAP Controller, and the register cells. The TAP Controller is a 16-state machine that controls the Boundary Register.
The TAP signals shown in the illustration are used to control the boundary scan device. They include the following:
• Test Data In (TDI): The serial input for test data and instruction bits.
• Test Data Out (TDO): The serial output for test data.
• Test Clock (TCK): An independent clock used to drive the device.
• Test Mode Select (TMS): This provides the logic levels needed to change the TAP Controller from state to state.
• Test Reset (TRST) Optional: This optional input provides asynchronous initialization of the TAP Controller, which in turn causes asynchronous initialization of other test logic included in the design.
Boundary scan devices can perform many test functions. Three of these, EXTEST, SAMPLE/PRELOAD, and BYPASS, are mandatory for every boundary-scan device. For other test functions, INTEST, RUNBIST, IDCODE, CLAMP, HIGHZ, and USERCODE, are described by the IEEE 1149.1 standard, but are optional. Manufacturers can also add test functions whose implementation is guided by the IEEE standard.
What is a BSDL file and how important is it in boundary scan?
A BSDL file, which is the acronym for Boundary Scan Description Language file, is a subset of Very High Speed IC Hardware Description Language (VHDL) that describes the boundary scan device package, pin description and boundary scan cell of the input and output pins. The BSDL file is very important in generating a boundary scan test. Without a BSDL file, it is impossible to generate any boundary scan test.
Boundary Scan DFT Guidelines: Rule#1: Pull-up or Pull-down resistors for Test Access Port (TAP)
It is very important for the TCK, TMS, TDI, TDO and TRST pins to be pulled up or pulled down by resistors during a boundary scan test. The resistors are there to prevent the IC from inadvertently entering into boundary scan mode or changing of states during a boundary scan test. In most cases, there are weak pull-ups and pull-downs designed into the IC, but external pull-ups and pull-downs are recommended. The recommended configuration is to pull up TDI, TDO, TMS and TRST with a 1.2kΩ (typical) resistor to Vcc and pull down TCK with a 100Ω resistor to ground. Users may refer to the IC design document for recommended resistance values from the IC Designer. The values of the pull-up or pull-down resistors may impact the overall power consumption. For example, lower pull-up or pull-down resistances require stronger external driver capabilities.
Boundary Scan Guidelines: Rule#2: Chaining up boundary scan devices for better test coverage and easier debug
Connect the TAP of each boundary scan IC into a daisy chain with the TDO of the first IC connecting to the TDI of the second IC, the TDO of the second IC connecting to the TDI of the third IC, and so on. The TMS and TCK ports are all shorted together with the traces running in parallel. It is important to design the TDI pin away from the TDO pin to avoid possible short circuit between the two. For long chains, the fan-out of the TCK and TMS need to be considered. Buffer circuitry could be placed within the chain to boost the signal across the chain. The order of the ICs within the chain is mostly determine by the location of the ICs. Where possible, place new and unverified boundary scan ICs at the ends of the chain. This is so that these components can be easily removed from the chain if necessary.
By chaining the boundary scan ICs together, it allows test signals to be passed between boundary scan ICs via the test cells (See (A) in Fig2). The tester does not need to drive or receive signals directly from these nodes; therefore, test points are not required.
Boundary Scan Guidelines: Rule#3: Test access where needed
Since the function of the boundary scan component is controlled by the TAP, it is critical that each TAP pin has a test point assigned. Without which, it is not possible to test the component using boundary scan. Where possible, it is good to assign probes on the TDI-TDO connections between the boundary scan ICs (See (B) in Fig3). These probes can be used to help improve the debug process by isolating the ICs that are difficult to debug from the chain. For the other pins on the boundary scan component, there should be at least one test point assigned. This is to validate that the component can be put into boundary scan mode and able to output correct signals (See (C) in Fig3). For certain boundary scan ICs, a number of pins (less than five pins) need to be activated in order to put the IC into boundary scan mode. These pins are called compliance-enable pins and they would require test access on each of them. The boundary scan standard includes syntax to add warning messages into the boundary scan description language (BSDL) file. The message could warn users of the need to use the compliance-enable pins for boundary scan testing.
Boundary Scan Guidelines: Rule#4: Using level shifters between ICs of different logic levels
Depending on the circuit design, there may be boundary scan ICs with TAPs of different logic levels that have to be connected together in a chain. Level Shifters need to be added to the chain between these ICs to manage the different logic levels.