Hi, I would like to seek advice on the attached test fixture used for measurement of my DUT. May I know if I design a calibration fixure similar to the attached test fixture with A+B=C, will I possibly remove the via effect using the AFR tool in PLTS?
If the scale is correct, probably not. If the lines on the top and bottom are long with respect to the board thickness, then you might get some reasonable results. You will need a "thru" fixture as well where the DUT is replaced with a thru. Is the drawing to scale? Or are the top and bottom board lines long?
Attached is calibration board that we intend to fabricate. We are really hoping to remove the effects of the transmission lines and vias. The transmission line is about 10x the board thickness. May I know if this is sufficient/effective?
With your dimensions AFR will give some reasonable result, but the trouble is the AFR presumes that the line impedance is the same on the left and right side of the DUT.
May I ask why, if the DUT is surface mounted, do you use a via to get to the second port, rather than just have both ports on the same side of the PCB? I ask this because in cases like yours, where the via must be used, it is often wise to include it in the DUT response if you have the situatuion that the DUT must always use a via. If you want to try to de-embed the via from the results, it might be better to make another test fixture with equal lines and measure just the via. U
If you must use a via, than just note that the via response will influence the results. If you make a "thru" fixture, you can like see the effect of the via through the time-domain response near the center of the thru line.
For any kind of pcb dut verification, you have an issue of defining the reference planes and impedances for the DUT, and the same DUT can have different behavior depending upon the particular implementation of the grounding used in the application.
Thank you very much for the insight in DUT calibration with regards to via de-embedding. We will study on your recommendation to build a separate test fixture to charaterize the via and to use it for de-embedding. Hope we can share the results soon. Thanks once again!