Thread: PNA-X configuration for power FETs model validation


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reseng

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PNA-X configuration for power FETs model validation
Posted: Mar 1, 2012 5:02 AM
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Hello,
We would like to order a N5242 for the purpose of FET (GaAs,GaN) models characterization (non X params). We also selected noise measurements option 029 which demands to order 219 or 285 power configuration. Option 219 provides build-in attenuators and a bias tees and 30 dBm limit on receiver port. Build-in bias tees has limitation 40V and 200 mA which is not enough for us so we choose to order external ones. If I understand right, typical procedure will be to measure S parameters at different biases at source power settings about -20 dBm -l -10 dBm. Expecting 15 dB gain we don't need external attenuators during parameters extraction measurements. To validate our extracted FET model we need to use a higher power signal. If we set 10 dBm source power at perfect match one can expect 25 dBm at receiver which is still below 30 dBm power limit.
1) Is it right setup for model validation measurements or we need some how to reduce amplitude using external attenuator somehow plugged in PNA-X receiver test set? Do we need external low loss directional couplers, signal generator and amplifier in the test set? Is N5242-285 option (20 W, no internal bias tees) will be a better solution then 219? Would you be so kind to clarify this question so we can order a right configuration of our measurements setup.
I saw pulsed solutions from Auriga and Amcad but for a moment they are not available for us.
2) Second question concerning noise figure measurements of a FETs using the wafer probe. ECal module is intended to find 50 Ohm input impedance NF, but to find minimum NF point at input impedance map most probable we need to use a tuner to get a lager map. The Maury noise characterization solution again is not for now. How we can use a manual tuner to obtain a noise figure of a FET? Do we need an ECal module for calibration in this setup?
3) Load pull measurements using manual tuners on wafer probe. If I understand right we need a microwave source, power amplifier, input tuner, probe station, output tuner, power meter. Should we use somehow a PNA-X and ECal in this setup for calibration or power measurements? Do we need couplers?
4) Is it possible to use Agilent B2902A source/measure unit connected to PNA-X through external bias-tees to measure DUT(FET) IV characteristics? DUT will be connected through RF probe. B2902 is intended to be used as a bias source during S parameters measurements, but if we can use it to measure IV at the same connection it will be good.

Thank you in advance,
Oleg Tokmakov
Dr_joel


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Registered: 12/01/05
Re: PNA-X configuration for power FETs model validation
Posted: Mar 1, 2012 7:57 AM   in response to: reseng in response to: reseng
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In reply (and thanks for considering the PNA-X) yes to everything.

1) 285 is probably the best option, but if you are in pulsed mode, really the internal bias tee can handle 10 W no problem as long as average power is lower. It is all heating. 285 gives more power (no loss from bias tee) and is often used for exacly your application. If you are doing pulsed measurements, then using the internal pulse modulator is very easy. Pulse profile is easiest with optioon 008.
2)maybe, maybe not. You can put the ecal right on the wafer probe station, if you can route a bypass switch around it to allow you to bypass it when you are making non-noise-figure measurements. In such a case, you can get the 50 ohm noise figures even with a poor match. There is information available from the PNA in the form of the noise-correlation matrix that with some math can be transformed into the minimum noise figure. THe results are best for well matched devices, but do pretty good for even poor match in some cases. You can look at this paper as a reference: http://ieeexplore.ieee.org/xpls/abs_all ... 5200&tag=1
3) Full load pull is really easiest done with a load pull system. For your power levels, you can probably use the PNA directly, but you have to know how to de-embed the tuners or use tuners with couplers after them. It's a lot of work to roll-your-own.
4)Yes. And in the next release of firmware (maybe in April), we will be able to control the B2900 directly from the PNA including setting and reading voltage and current. I'm working on that right now.
reseng

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Registered: 02/16/12
Re: PNA-X configuration for power FETs model validation
Posted: Mar 1, 2012 9:44 AM   in response to: reseng in response to: reseng
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Thank you for your answer, Dr_joel.
I thought Pulsed RF without pulsed bias will not help to avoid FET self heating. Is it possible to get pulsed bias just having option 008 and internal PNA bias sources without external pulsed system (pused heads, high power sources)?
Dr_joel


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Registered: 12/01/05
Re: PNA-X configuration for power FETs model validation
Posted: Mar 1, 2012 11:45 AM   in response to: reseng in response to: reseng
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Sorry, no, you still have to have a pulsed-biased system depending upon your design. But you can use the internal pulse-generator to drive and gate pulsed bias systems, depending upon current and speed needs. To avoid RF overheating of the VNA parts, using pulsed RF will allow the average power to be lower on the VNA components that care about power such as the dc bias tee.
reseng

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Registered: 02/16/12
Re: PNA-X configuration for power FETs model validation
Posted: Jun 29, 2012 8:38 AM   in response to: Dr_joel in response to: Dr_joel
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Hello,
Our colleagues found that even 500ms pulsed bias is helpful in achieving higher power levels during on-wafer S-parameters measurements. Such pulse lengths should be available using B2902A Series Precision Source / Measure Unit. Is it possible to synchronize somehow N5242 and B2902A to perform quasi bias pulsed S-parameters measurements? I.e. pulsed bias synchronized with pulsed RF on about 500ms pulse lengths. If it's possible, would you be so kind to give me hint (or link to documentation) how to do this? We have ordered PNA-X with N1966A pulse I/O adapter option without pulsed (008) option.

Dr_joel wrote:
And in the next release of firmware (maybe in April), we will be able to control the B2900 directly from the PNA including setting and reading voltage and current. I'm working on that right now.

Regards,
Oleg Tokmakov
reseng

Posts: 14
Registered: 02/16/12
Re: PNA-X configuration for power FETs model validation
Posted: Jun 29, 2012 10:24 AM   in response to: reseng in response to: reseng
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In this document
http://cp.literature.agilent.com/litweb/pdf/5990-6895EN.pdf
I found the following
"In addition, the B2900A Series and network analyzer’s external trigger inputs and outputs are connected to each other, and the trigger signals are used to improve overall system performance."
It looks like something that I need.
Could you tell me there I can find a details about connectivity (which cables do we need to connect trigger inputs) and software needed to perform such things?
Dr_joel


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Registered: 12/01/05
Re: PNA-X configuration for power FETs model validation
Posted: Jun 29, 2012 1:00 PM   in response to: reseng in response to: reseng
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This is exactly what we hope to do, and now maybe we good incentive to look closely at this. I think it can be done, and with the B2900, the pulse widths can be made quite narrow, maybe less than 0.1 msec which would be good for your situation. I will work some more with the software team to see if we can sort out how to do the pulse synch in just the way you propose, but it is a little tricky, I think. We just need to sort out all the setup and triggering initialization commands.
reseng

Posts: 14
Registered: 02/16/12
Re: PNA-X configuration for power FETs model validation
Posted: Aug 22, 2012 9:20 AM   in response to: Dr_joel in response to: Dr_joel
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Hi Dr_joel,
Could send me a note if you succeed with pulse triggering? During installation of our new Agilent hardware we’ve try to run PNA with B2900 in synchronized sweep mode (no pulses, just like 5990-6895EN.pdf) but without success. Agilent Moscow specialists used MEAS TIRG RDY and MEAS TRIG IN PNA connection to the DIGITAL I/O of B2900. They checked physical connection (pins) and trigger pulses with oscilloscope and told me that connection is ok. As I understand problem is that B2900 after receiving a trigger signal from PNA (RF meas complete) do not start next step of bias sweep.
My PNA has options 029,200,285 which is as I understad is equal 029,200,219,H85. I found +30 dBm warning labels on front panel under RF test ports 1 and 2. Is it ok? According documentation Test Port damage level (without jumpers) must be 43 dBm and 30 dBm with jumpers. Does “without jumpers” means here that one must insert in RF path suitable (according H85 ap.note) attenuation?
Regards,
Oleg

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