All signal inputs to the ATC2 state core are registered and clocked on the edge you specify. Internal to the core, the registered value of signal 1 is passed to the logic analyzer on the rising edge of the clock, and the value of signal 2 is passed to the logic analyzer on the falling edge of the clock. The logic analyzer uses a de-multiplexing mode to decompress the information and preserve all triggering and analysis capabilities
For example: If you have ATC2 signal banks with 64-bit width, the simultaneous measurement of 64 signals requires 32 FPGA pins and 64 logic analysis channels. Only 32 of the logic analysis channels are physically connected to pins of the FPGA. The other 32 channels provide their acquisition memory and triggering resources for the measurement.