Download the Technical Information Package for W1714 AMI Modeling Kit
Learn how to use an electronic system-level (ESL) workflow to not only optimize your SERDES design at the behavioral level, but also automatically generate ANSI/EIA-656 IBIS Algorithmic Modeling Interface (AMI) compliant models for your SERDES chip.
- Rapidly optimize the signal processing at the appropriate level of abstraction (i.e. behavioral level)
- Implement the optimized architecture one time
- AMI is a natural by-product of the architectural model
Please fill out and submit the form below to download the Technical Information Package, which contains full details about the W1714 AMI Modeling Kit.
Learn how to cut through the challenges of today's multi-gigabit standards. Watch this short video on the Agilent EEsof High Speed Digital Design Flow.
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